The present invention relates to an H-bridge drive circuit, and more specifically, to a method and circuit for controlling the drive of transistors in an H-bridge circuit.
In the prior art, an H-bridge circuit is incorporated, for example, in a motor driver for driving a motor (load) or a switching regulator for supplying power to an internal circuit (load) of an LSI. The H-bridge circuit is also referred to as a full-bridge circuit and normally includes four transistors. Japanese Laid-Open Patent Publication No. 2000-82946 describes an H-bridge circuit having a different configuration. This H-bridge circuit includes six transistors.
FIG. 1 is a schematic circuit diagram of a prior art H-bridge circuit 100 using four transistors The H-bridge circuit 100 includes four transistors T1, T2, T3, and T4. The transistors T1 to T4 are each formed by an N-channel MOS transistor and connected between a first power supply VM (e.g., 5V power supply) and a second power supply PGND (e.g., ground (0V)).
The first transistor T1 has a drain connected to the first power supply VM, a source connected to a first output terminal 102, and a gate receiving a first drive voltage topA. The second transistor T2 has a drain connected to the first output terminal 102, a source connected to the second power supply PGND, and a gate receiving a second drive voltage botA. Accordingly, the first and second transistors T1 and T2 are connected in series between the first and the second power supplies VM and PGND, and the first output terminal 102 is connected between the first and the second transistors T1 and T2.
The third transistor T3 has a drain connected to the first power supply VM, a source connected to a second output terminal 104, and a gate receiving a third drive voltage topB. The fourth transistor T4 has a drain connected to the second output terminal 104, a source connected to the second power supply PGND, and a gate receiving a fourth drive voltage botB. Accordingly, the third and fourth transistors T3 and T4 are connected in series between the first and the second power supplies VM and PGND, and the second output terminal 104 is connected between the third and the fourth transistors T3 and T4.
A motor 110 serving as a load is connected to the first output terminal 102, which is located between the first and the second transistors T1 and T2, and the second output terminal 104, which is located between the third and the fourth transistors T3 and T4. The H-bridge circuit 100 of FIG. 1 is used as a motor driver for driving the motor 110.
The first to fourth transistors T1 to T4 are driven by the first to fourth drive voltages topA, botA, topB, and botB, which are generated by a control circuit (not shown). The first and fourth transistors T1 and T4 define a first set, and the second and third transistors T2 and T3 define a second set. The control circuit generates the drive voltages topA, botA, topB and botB so that the first set of the transistors T1 and T4 and the second set of the transistors T2 and T3 are activated and inactivated in a complementary manner.
When the first and fourth transistors T1 and T4 are activated by drive voltages topA and botB having an H level, the second and third transistors T2 and T3 are inactivated by drive voltages botA and topB having an L level. In this state, a first current path is formed extending through the first transistor T1, the motor 110 (load), and the fourth transistor T4 between the first and the second power supplies VM and PGND. Accordingly, a first output voltage OUTA applied to the first output terminal 102 causes the motor 110 to generate rotation in a first direction (e.g., forward direction).
When the second and third transistors T2 and T3 are activated by the drive voltages botA and topB having an H level, the first and fourth transistors T1 and T4 are inactivated by the drive voltages topA and botB having an L level. In this state, a second current path is formed extending through the third transistor T3, the motor 110 (load), and the second transistor T2 between the first and the second power supplies VM and PGND. Accordingly, a second output voltage OUTB applied to the second output terminal 104 causes the motor 110 to generate rotation in a second direction (e.g., reverse direction), which is opposite the first direction.
In this manner, the H-bridge circuit 100 changes the direction of the voltage to be applied to the motor 110 by a single power supply (first power supply VM) and controls the drive of the motor 110.
FIG. 2 is a timing diagram showing a drive sequence for controlling the H-bridge circuit 100 of FIG. 1. The drive sequence of the prior art includes a first driving step for driving the motor 110 with the first current path, a second driving step for driving the motor 110 with the second current path, and a switching step for switching between the first and the second current paths.
In the first driving step, the first and fourth drive voltages topA and botB rise to an H level to activate the first and fourth transistors T1 and T4. As a result, the first output voltage OUTA (approximately 5V) is applied to the first output terminal 102, and the motor 110 is driven in the first rotating direction.
In the second driving step, the second and third drive voltages botA and topB rise to an H level to activate the second and third transistors T2 and T3. As a result, the second output voltage OUTB (approximately 5V) is applied to the second output terminal 104, and the motor 110 is driven in the second rotating direction.
In the switching step, the first to fourth drive voltages topA, botA, topB, and botB are set to an L level, and the first to fourth transistors T1 to T4 are all inactivated. The switching step switches the first to fourth transistors T1 to T4 to prevent shoot-through current from flowing through the transistors T1 and T2 or shoot-through current from flowing through the transistors T3 and T4. Such a switching step is also referred to as an OFF-OFF period or dead time.
However, switching noises such as undershoots A1 and A2 or an overshoot B1 are produced in the switching step (OFF-OFF period) of the prior art sequence shown in FIG. 2. The undershoots A1 and A2 are caused by back electromotive force (BEMF) of the motor 110. For example, even when the first and fourth drive voltages topA and botB fall to an L level from an H level and inactivate each of the transistors T1 to T4, the motor 110 continues the flow of current from the first output terminal 102 to the second output terminal 104. Accordingly, current supplied from the second power supply PGND through a parasitic diode between the source and drain of the second transistor T2 lowers the first output voltage OUTA from the second power supply voltage PGND, or the ground level. More specifically, the first output voltage OUTA is lowered from the ground level by a level corresponding to the voltage drop (hereafter referred to as diode drop) VF at the parasitic diode of the second transistor T2. This generates an undershoot A2 in the waveform of the first output voltage OUTA. In this state, the parasitic capacitor between the source and gate of the first transistor T1 also lowers the first drive voltage topA by a level corresponding to the diode drop VF. This generates an undershoot A1 in the waveform of the first drive voltage topA. Further, the current that flows from the motor 110 to the second output terminal 104 tends to flow to the first power supply VM through the parasitic diode of the third transistor T3. Accordingly, the second output voltage OUTB is raised from the first power supply VM by a level corresponding to the diode drop VF of the third transistor T3. Such switching noises A1, A2, and B1 are generated in the same manner when shifting from the second drive step to the switching step.
The occurrence of the switching noises A1, A2, and B1 is a phenomenon unique to motor control and H-bridge circuits. The power for recent LSIs has been lowered to an ultra-low level. Thus, when a plurality of functional blocks is mounted on the same chip like in a System On a Chip (SOC) the above switching noises may affect not only the operation of one functional block but also the operation of other functional blocks.
It would be advantageous to have an H-bridge drive circuit and an H-bridge driving method that reduce switching noise while preventing shoot-through currents from flowing through the H-bridge circuit.